module test1(i1,i2);
input i1, i2;
reg [31:0] a;

	always @(i1) begin
		#1 a = 1;
		#5 a = a + 1;
		#5 a = a + 2;
	end

	always @(i2) begin
		#1 a = 10;
	end

	initial begin
		$monitor ($time, "\t a = %d", a);
		a = 2;
	end

endmodule

module testtest1();

	reg i1, i2;

	test1 t1(i1,i2);

	initial begin
		i1 = 1;
		#2 i1 = 0;
		#10 $finish;
	end

endmodule