Using Synopsys' Verilog Compiler - VCS 7.1.2

This document provides an overview for new users of the Verilog compiler VCS.

Verifying your VCS installation

This tool is currently setup to run interactive.cs.tamu.edu (also named unix.cs.tamu.edu). To verify whether the tool is installed or not, enter the following on the command prompt:

    # which vcs                              (Hit enter)
    /opt/apps/bin/vcs                  (You should see this displayed on the next line)

If you get a command not found message, you may need to setup the tool for your account (Once again, this will only work on interactive/unix). On the command prompt, start the bash shell as follows:

    # bash                                                                                                                                (Hit enter)
    bash-3.00$ . /usr/local/bin/synopsys.shell.source.bash        (Hit enter)

Now check to see if the environment variables VCS_HOME, LM_LICENSE_FILE have been set or not. You can do this my using the echo command.
Running the "which vcs" command should now show the path to the VCS executable. If this still gives an error message, please check with your TA.

Compiling your Verilog files

Once you have created a Verilog file, you can compile it with the 'vcs' command. On the command prompt enter the following command:

    # vcs <Verilog file 1> <Verilog file 2> ...

If your code has no errors, the compiler will generate an executable simv which when run will display the outputs generated by your code. To avoid this two step process you can simply add the "-R" flag to have the compiler execute your code once it compiles successfully.

Apart from the outputs generated from your code, VCS also displays other information like version, time units for which the Verilog code executed, CPU time used, etc.

Using Virsim - an interactive debugging environment

The Synopsys package also includes an interactive debugging environment - Virsim - that can be used in conjunction with VCS. To invoke the GUI, compile your Verilog files with the "-I" option, i.e.

    # vcs -RI <Verilog file 1> <Verilog file 2> ...

This will invoke the GUI. (Under the help menu of Virsim, you will find an option for 'VCS manuals'. Detailed information on using VCS and Virsim can be found there.)

Through this interface, you can examine the waveforms of all the signals within the system (Waveform window), the flow of signals between the different modules in your system (Logic browser), follow the flow of execution of the Verilog source code (Source viewer). The Hierarchy browser can display the composition of your system in the form of a tree structure. You can select different modules and their signals and view them in either of the aforementioned forms.

So if you wanted to examine the waveforms of the output signal of a particular module,

•     select that module in the Hierarchy browser (HB),
•     open a waveform window (WW),
•     using your middle mouse button drag the desired signal from the HB to the WW.
•     Now hit the green arrow on the main Virsim window and the WW will display the signal level changes.

Try out the different button/options once you have a working design. Virsim can be a very useful tool (rather than using a number of $display command - the printf() of Verilog), especially when you care debugging complex design with intricate signal flows.