CPSC/ECEN 680
Homework
Homework is due at the end of the day specified in the instructor's office (or slid under the door). Homework is to be done individually. You may discuss the problems in general. Unless otherwise noted, all problems are out of System on Chip Test Architectures. At their request, solutions to problems from the textbook will be handed out in class rather than posted on the Web site.
Each homework problem carries equal weight. For problems that are asking for a qualitative answer, e.g. “why is BIST better than X?” cover the most important points, but do not attempt to give an exhaustive answer. Some problems may require you to look up references cited in the corresponding chapter in order to obtain enough information to solve them.
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Homework |
Due Date |
Topic |
Problems |
|
1 |
2/28/08 |
Introduction, Test Architectures, Fault Tolerance |
1.1, 1.3, 1.5, 1.11, 1.14, 2.1, 2.3, 2.6, 2.10, 2.12, 2.18, 3.1, 3.3, 3.10 |
|
2 |
5/5/08, Optional for extra credit |
NoC Test, Delay Test, Low Power Test, Physical Failures, FPGA Test, High-Speed I/O Test, Fault Simulation, Testability, Combinational ATPG, Sequential ATPG |
4.1, 6.4, 7.1, 8.1, 12.1, 14.2, Explain how SCOAP metrics are related to combinational and sequential testability. Explain the difference between the D, PODEM and FAN algorithms. Given an example showing FAN with better performance than PODEM or D. What is the drawback of time-domain expansion for sequential ATPG of deeply sequential circuits? |
This page last updated on February 19, 2008. Please send any problems to Hank Walker