CPSC/ECEN 680 Project

Out: 4/1/2008

Due: 5/5/2008 by end of day

Project Procedure

Assignment

The project is to study BIST approaches for single stuck-at faults in combinational logic circuits, to identify the best choices in terms of fault coverage, test pattern count and hardware complexity for different circuits. You will not consider output response analysis. You will do paper designs of BIST hardware and then simulate them in software to generate test patterns, which you will then evaluate in terms of fault coverage.

You will use the FSIM PPSFP (parallel pattern, single fault propagation) fault simulator from Dong Ha at Virginia Tech, and the ISCSAS85 benchmark circuits. You will design BIST circuits to generate pseudo-random patterns. Rather than simulating this BIST hardware directly, you will write programs that produce the same behavior, to generate test patterns. You will then evaluate the fault coverage of these patterns on the benchmark circuits.

The files for this project are located in /user/walker/Public/cpsc680. See the README files in various subdirectories. The fault simulator is located in the fsim subdirectory. The ISCAS85 benchmarks are located in the ISCAS85 benchmark directory. The ATALANTA stuck-at combinational ATPG is located in the atalanta directory. The SOPRANO stuck-open combinational ATPG is located in the soprano directory, but we are not using it in this project The ATALANTA-generated test vectors and their statistics for the ISCAS85 circuits are located in the ISCAS85 directory, so it is not necessary for you to run the ATPG tools. These tools are compiled for Sun SPARC/Solaris (e.g. sun.cs.tamu.edu). If you are an ECE student, and do not have a CS account, then the easiest solution is to copy these files to an ECE UNIX server and recompile FSIM.

FSIM has the ability to generate random patterns and fault-simulate them. You can use this capability to test your own code on for pure pseudo-random numbers, and use it as a comparison for more intelligent BIST approaches.

Your project should consider the following BIST approaches, design the appropriate BIST hardware for each ISCAS85 circuit, write software to generate test patterns for that behavior, and evaluate the fault coverage of the patterns.

  1. Pseudo-random patterns generated by an LFSR, applied in parallel to the design (test per clock). Thus, the LFSR should have the same number of outputs as the inputs to the circuit. Use a reasonable polynomial of your choosing and justify your selection (e.g. it uses minimum XOR gates). You can find tables of primitive polynomials on the Web (e.g. search for “table of primitive polynomials”).
  2. Try reseeding the LFSR a number of times with random values and repeating the analysis above. Are the results very sensitive to the initial seed? Remember that in a standard LFSR, a seed of all zeros causes the LFSR to stay at all zeros.
  3. Pseudo-random numbers generated by an LFSR, applied via a scan chain (LFSR output feeds a scan chain). Assume that the scan chain order is the same as the primary inputs, with the bits being scanned from input 1 to input N. The bits are fed into the scan chain from one of the outputs of the LFSR, commonly the rightmost bit, assuming bits are shifted left-to-right in the LFSR. You will apply the patterns in two ways. In the first approach, each new pattern is just a one-bit shift of the previous pattern (with the new input bit), so after each shift you capture the results and read them out. This is related to the test-per-clock approach. In the second approach, you fill the entire scan chain with LFSR outputs before capturing the results. This is the test-per-scan approach. The drawback of the one-bit shift approach is the correlation from pattern-to-pattern, but the advantage is less shift time. Note that unlike the parallel LFSR of test-per-clock, the LFSR in this case does not have to be as long as the scan chain, and if usually much shorter. Try to find the smallest (fewest bits) LFSR that achieves close to the maximum fault coverage in each pattern application approach .
  4. Try modifying the weights for the LFSR feeding a scan chain so that the probability of an input bit being a 0 is 0.25 and 0.75, instead of 0.5. For example, ANDing two random bits (probability 0.5) will make an output that is zero with probability 0.75. Using the test-per-scan approach, what are the fault coverage results for the two different weights? Apply all three weights in sequence - 0.5, 0.25, 0.75, using for each one only ~1/3 the patterns you used for one weight by itself. Does this give you higher coverage than one weight alone? Can you use fewer vectors to get the same coverage as one weight?

In each case, determine the ultimate fault coverage, fault efficiency and number of patterns and clock cycles for pattern application to achieve maximum fault coverage. Although you do not have to build it, assume the outputs are compressed into a MISR, so ignore the time to read out the test results, and only consider test application time. Consider the ATALANTA fault coverage results to be the upper bound of achievable fault coverage. You might find it useful to use FSIM's random fault simulation capability to study some of these issues before generating LFSR patterns. It might be helpful to plot fault coverage vs. number of patterns applied, to see when the rate of finding new faults is so low that it is unlikely additional faults will be found. This also helps to identify random-pattern resistant faults, and guide your weighted random pattern work.

The writeup should not include large listings of fault simulation or ATPG output, or listings of the program you use to generate your LFSR patterns. Instead you should summarize results in tables, plots, etc., with diagrams of LFSR approaches, the polynomials selected, with a discussion of your design approaches and an analysis of the results.