CPSC/ECEN 680: Testing and Diagnosis of Digital Systems

Location

Lecture: HRBB 113 TR 9:35-10:50am

Text

· System on Chip Test Architectures, Wang, Stroud, Touba (ed.), Morgan Kaufmann, Burlington MA, 2008, ISBN: 978-0-12-373973-5.

· Supplemental papers.

Catalog Description

The theory and techniques of testing VLSI-based circuits and systems, and design for testability.

Course Summary

This course introduces the test problem, the test process and test economics. It covers the problems of testing integrated circuits, the design of circuits for testability (DFT), the design of built-in self-testing (BIST) circuits, and diagnosing defective circuits. A typical circuit in 2008 contains several million gates. A microprocessor contains nearly a billion transistors and many kilometers of wiring. Testing determines whether the circuit works correctly and reliably. The processes involved in testing include fault modeling, fault simulation and test generation for combinational, sequential and mixed signal circuits. Specialized techniques are available for testing memories. DFT/BIST is necessary since adequate testing of large designs is intractable or expensive without circuitry to simplify the problem.

Grading

Homework	25%
Paper	20%
Project (Team)	30%
Final Exam	25%

Grades are assigned based on the standard method. If necessary a curve will be used.

Policies

Prerequisites: ECEN 248 or equivalent; CPSC 321 or ECEN 350 or equivalent; You need to know C/C++ programming, Boolean algebra, discrete algorithms, data structures, combinational and sequential logic and circuit design, electrical network theory, and computer architecture, as covered in the undergraduate computer engineering program.

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