# load configuration from a file
# -config               

# dump configuration to a file
# -dumpconfig           

# print help message
# -h                          false 

# verbose operation
# -v                          false 

# enable debug message
# -d                          false 

# start in Dlite debugger
# -i                          false 

# random number generator seed (0 for timer seed)
-seed                             1 

# initialize and terminate immediately
# -q                          false 

# restore EIO trace execution from <fname>
# -chkpt                     <null> 

# redirect simulator output to file (non-interactive only)
# -redir:sim                 <null> 

# redirect simulated program output to file
# -redir:prog                <null> 

# simulator scheduling priority
-nice                             0 

# maximum number of inst's to execute
-max:inst                         4294967200 

# number of insts skipped before timing starts
#-fastfwd                          0 

# generate pipetrace, i.e., <fname|stdout|stderr> <range>
# -ptrace                    <null> 

# instruction fetch queue size (in insts)
#-fetch:ifqsize                    16 

# extra branch mis-prediction latency
#-fetch:mplat                      7

# speed of front-end of machine relative to execution core
#-fetch:speed                      1 

# branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}
#-bpred                        comb 

# bimodal predictor config (<table size>)
#-bpred:bimod           2048 

# 2-level predictor config (<l1size> <l2size> <hist_size> <xor>)
#-bpred:2lev            2 2048 11 1 

# combining predictor config (<meta_table_size>)
#-bpred:comb            2048 

# return address stack size (0 for no return stack)
#-bpred:ras                        16 

# BTB config (<num_sets> <associativity>)
#-bpred:btb             512 4 

# speculative predictors update in {ID|WB} (default non-spec)
# -bpred:spec_update         <null> 

# instruction decode B/W (insts/cycle)
#-decode:width                     8 

# instruction issue B/W (insts/cycle)
#-issue:width                      8 

# run pipeline with in-order issue
#-issue:inorder                false 

# issue instructions down wrong execution paths
#-issue:wrongpath               true 

# instruction commit B/W (insts/cycle)
#-commit:width                     8 

# register update unit (RUU) size
#-ruu:size                        128 

# load/store queue (LSQ) size
#-lsq:size                         64 

# l1 data cache config, i.e., {<config>|none}
-cache:dl1             dl1:64:32:1:l 

# l1 data cache hit latency (in cycles)
#-cache:dl1lat                     1 

# l2 data cache config, i.e., {<config>|none}
-cache:dl2             ul2:256:128:1:l 

# l2 data cache hit latency (in cycles)
#-cache:dl2lat                     20 

# l1 inst cache config, i.e., {<config>|dl1|dl2|none}
-cache:il1             il1:64:32:1:l 

# l1 instruction cache hit latency (in cycles)
#-cache:il1lat                     1 

# l2 instruction cache config, i.e., {<config>|dl2|none}
-cache:il2                    il2:256:128:1:l 

# l2 instruction cache hit latency (in cycles)
#-cache:il2lat                     20 

# flush caches on system calls
#-cache:flush                  false 

# convert 64-bit inst addresses to 32-bit inst equivalents
#-cache:icompress              false 

# memory access latency (<first_chunk> <inter_chunk>)
#-mem:lat               100 5 

# memory access bus width (in bytes)
#-mem:width                        8 

# instruction TLB config, i.e., {<config>|none}
-tlb:itlb              itlb:32:4096:4:l 

# data TLB config, i.e., {<config>|none}
-tlb:dtlb              dtlb:1:4096:32:l 

# data TLB L2 config, i.e., {<config>|none}
-tlb:dl2tlb           dl2tlb:1:4096:128:l 

# inst/data TLB miss latency (in cycles)
#-tlb:lat                         200 

# total number of integer ALU's available
#-res:ialu                         4 

# total number of integer multiplier/dividers available
#-res:imult                        2 

# total number of memory system ports available (to CPU)
#-res:memport                      2 

# total number of floating point ALU's available
#-res:fpalu                        2 

# total number of floating point multiplier/dividers available
#-res:fpmult                       1 

# profile stat(s) against text addr's (mult uses ok)
# -pcstat                    <null> 

# operate in backward-compatible bugs mode (for testing only)
#-bugcompat                    false 

# L1 instruction victim cache {none|<nvictims>}
#-cache:il1:vb                     4

# L1 data victim cache {none|<nvictims>}
#-cache:dl1:vb                     4