How to Use Makefile
Before you can use the utility “make”, you need to
prepare a file called “makefile” or “Makefile”
that describes the relationships among files in your program and states
the commands for creating or updating each file. Typically the executable
file is created from object files (ending with .o), which,
in turn, are created by compiling C source files (ending with .c).
Invoking the command make is sufficient to perform all necessary
compilations.
Makefile Example.
Here is a simple example showing how to write makefile. Any
comment starts with the character # (hash) and ends at the
line end.
The command line must start with a tab (on your keyboard it is usually
the key Tab). Below we will write the word TAB to denote
a tab (because it is invisible). Please, do not write the
word TAB in your examples – here the
word TAB is used only to show you where a tab should go.
A tab is usually equivalent to a sequence of 8 spaces but do not replace
a tab with a space (or several spaces) because it will not work.
Also if a line is too long it can be split into two (or more) lines
by using the character \ (backslash) and pressing
the key Enter (newline) immediately after the backslash. We assume
that to create makefile you use one of the standard UNIX
text editors (such as vi or emacs) or equivalent (such as pico).
In this example, all C files include the header file defs.h.
We assume that we are going to compile the following C files: main.c,
kbd.c, display.c. The executable file is
called edit.
-
# Makefile starts here
edit: main.o kbd.o display.o
TAB cc -o edit main.o kbd.o \
TAB display.o
main.o: main.c defs.h
TAB cc -c main.c
kbd.o: kbd.c defs.h
TAB cc -c kbd.c
display.o: display.c defs.h
TAB cc -c display.c
clean:
TAB rm edit main.o kbd.o display.o
make
or
make edit
To use this makefile to delete the executable file edit
and all the object files, you need to type
make clean
The target clean is not a file but merely the name of an
action. It is not dependent on any other rule. These kinds of target
are called “phony targets”.
Variables in Makefile.
Here is an example of a more complex makefile where we are
going to use variables.
-
# Use the variable "objects"
objects = main.o kbd.o display.o
edit: $(objects)
TAB cc -o edit $(objects)
main.o: main.c defs.h
TAB cc -c main.c
... # the rest is the same
clean:
TAB rm edit $(objects)
Implicit rules.
There is an implicit rule for updating an object file from a C source
file. Therefore we can use the following makefile:
-
# Another example
objects = main.o kbd.o display.o
edit: $(objects)
TAB cc -o edit $(objects)
$(objects): defs.h
clean:
TAB rm edit $(objects)